ATE (Automated Test Equipment) test boards are the core carriers of semiconductor testing, which can be divided into three categories according to the test stage and functional differences:
Probe Card
Ultra-high-density interface: BGA pitch (ball grid array spacing) up to 40-55μm (high-end products), and MLO/MLC adapter boards with packaging substrate process are required to achieve signal transmission.
Flatness control: Warpage rate ≤ 0.1%-0.2%, and the height difference of the pad in the BGA area is ≤ 25μm (strict scenarios) to ensure precise contact between the probe and the pad.
Signal integrity: impedance tolerance ±5%, stub length ≤ 12mil, which requires extremely high coating uniformity and back drilling process.
Application scenario: Wafer testing (CP testing), screening the electrical parameters of each chip on the uncut wafer.
Technical features:
负载板（Load Board）
Multi-layer high-density design: The number of layers is usually ≥ 30 layers, BGA pitch 0.35-0.5mm, and the drilling-to-conductor distance is <4mil.
Parallel testing capabilities: Support 4-16 test channels (Sites) to improve testing efficiency.
High-speed signal requirements: For high-speed interface ICs (such as SerDes), impedance matching and signal attenuation need to be strictly controlled.
Application scenario: Final test (FT test) of the chip after packaging to verify the function and performance of the chip.
Technical features:
老化测试板（Burn-in Board, BIB）
High-temperature resistant materials :P CB materials are required to withstand high temperatures for a long time (usually ≥ 125°C) and have high reliability.
Special structure design: such as Gold Finger for high-frequency signal transmission, hole-to-line distance ≤ 3.5mil.
Application scenarios: Aging testing of post-packaging chips, exposing early failure through thermal cycling or accelerated switching cycles.
Technical features: